TY  - DATA
AU  - Messmer, HansPeter
TI  - The indispensable PC hardware book
SN  - 0-201-59616-4
PY  - 2002///
CY  - Boston, Mass.
PB  - Addison-Wesley
N1  - Apéndices, glosario e índice alfabético, al final del libro; Basics
; The main components of a PC:
The computer and peripherals-Inside the personal computer:How to open the case.Protecting yourself against electric shocks.Data flow inside the PC.The motherboard.Graphics adapters and monitors.Drive controllers,floppies and hard disck.CD-ROM,CD-R and CD-RW.Parallel ports and printers.Serial ports and modems.Network adapters and LANs.CMOS RAM and realtime clock.Keyboard.Mice and other pointing devices.The power supply-Documentation-Looking after data and users-The operating system,BIOS,and memory organization:Is everything better with windows?.Windows and what it can do to hardware devices
; The PC's microprocessors
; Introduction to microprocessor technology:The field-effect transistor-Basics of machine-related information representation:Decimal and binary systems.ASCII code.Negative integers and two'scomplement.Hexadecimal numbers.BCD numbers.Little endian format and Intel notation-Logic gates:Basic logical elements.CMOS inverters as low-power components.An example:1-bit adder-The CPU as the core of all computers.
Everything began with the ancestor 8086:Pins and signals in the 8086-8086 operating modes and the 8288 bus controller-8086 real mode-Accessing the memory-Word boundaries-Accessing the I/O address space-8086 reset-The 8088-The 80186/88
Downwards compatibility-the 80286:Pins and signals in the 80286-The 80286 registers-80286 protected mode:80286 memory management registers.80286segment descriptors.80286 segment and access types.Multitasking,80286 TSS,and the 80286 task gate.80286 protection for I/O address space-80286 bus cycles and pipelining-Word boundaries-80286 reset.
Introduction to the world of 32-bitcomputing-the 80386:Pins and signals in the 80386-Access to physical memory and the ports:Bus cycle for read access.Bus cycle for white access.Wait states.Address pipelining or pipelined addressing.Double word boundary.Special cycles.Data bus and write data duplication.I/O address space and the peripherals.I/O addressing.I/Ocycles-Registers:Registers overview.Segmenting.General purpose and segment registers.Flags.Control and memory management registers.
Programing and operating types:Code segment and instruction counter-Stack segment and stack pointer-Data segment DS and addressing-Addressing types and instruction coding:Programming at processor level:mnemonics and the assembler.Adressing types and instruction coding.Loading instructions and prefetching-Real mode,high memory area,and HIMEM.SYS-Interruptsand exceptions:Software interrupts.Hardware interrupts.Exceptions-Protected mode:Segment selectors,segment descriptors,and privilege levels.Global and local descriptor tables.Switching into protected mode.Memory addressing in protected mode.Control transfer and callgates.Interrupt descriptor table.Multitasking,TSS,and task gates.Protecting the I/O address space.Protected mode exceptions and protection mechanisms-Paging:Logical linear,physical addressing,and paging.Page directory,page tables,and page frames.Test registers TR6 and TR7-Virtual 8086 mode:Virtual machines and virtual 8086 monitors.Addresses in virtual 8086 mode.Entering and leaving virtual 8086 mode.Tasks in virtual 8086 mode.
Quick buffering :caching:Cache principle and cache strategies-Cache organization and associative memory (CAM)-Cache hit determination and optimum cache size-Replacement strategies-On-chip and second-level caches-Cache consistency and the MESI protocol:The four MESI states.MESI state transitions.L2 cache sub-systems and the MESI cache consistency protocol-Pipelined burst cache.
All in one-the i486:Pins and signals of the i486-Internal structure of the i486-RISC or CISC:Microcoding.Back to basics.RISC characteristics and hardware level-The pipeline-The on-chip cache-Differences and common attributes of i486 and 80386/80387:Differences in register structures.Differences in memory management.i486 reset.i486 real mode.i486protected mode.i486 virtual 8086 mode.Integer core and floating-point unit.FPU exceptions.Translation lookaside buffer (TLB)-The i486 bus:Burst cycles.Special cycles.Invalidation cycles-Test functions:BIST internal self-test.Testing the TLB.Testing the on-chip cache.Tristate test mode.JTAG boundary scan test-The i486's address space
; Memory, chipsets, and support chips; Personal computer architectures and bus system; Mass storage and its interfaces; External and peripheral devices
ER  -